Diamond Wafer Application: Vertical 3D diamond field-effect transistors

Recent studies have shown that diamond field effect transistors (FETs) have great potential in high-power and high-frequency electronics, exhibiting a maximum

leakage current of 1.35 A⋅mm− 1 and a breakdown voltage of 2 kV. However, there is still a lack of preliminary exploration on diamond FETs with a three-dimensional (3D) architecture, which has been evidenced as a promising approach to increasing device performance and density for silicon transistors. Here, we present a systematic investigation of 3D vertical gate-all-around (GAA) diamond transistors, combined with numerical simulation, device fabrication, and characterization of device performance. The p-type conductivity of the diamond channel in a transistor is obtained by Boron-ion implantation. Our numerical

simulations address the close correlation of transfer characteristics of the 3D vertical GAA diamond transistors with the ion-implanted impurities. In the device fabrication, we introduce the focused ion and electron beam technology for the electrode interconnections in the 3D devices. Finally, we demonstrate that the 3D vertical GAA diamond transistor exhibits the on-off ratio of 2.5 × 103, subthreshold swing of 334.3 mV⋅dec− 1, and a threshold voltage of 0.64 V. And the temperature dependence of transfer characteristics of the 3D devices indicates that 3D vertical GAA diamond transistors have potential application prospects in extreme environments such as high temperatures.

Diamond has great potential to be applied for high-temperature, high-power, and high-frequency electronics, owing to its ultra-wide bandgap (UWBG, Eg = 5.47 eV) along with the large breakdown field, fast electron saturation velocity, high carrier mobility, and outstanding thermal conductivity. In comparison with other important WBG (GaN and SiC) and UWBG (AlxGa1-XN and β-Ga2O3) materials, diamond possesses higher carrier mobility (3800 cm2⋅V− 1⋅s− 1 for the hole and 4500 cm2⋅V− 1⋅s− 1 for electron) and thermal conductivity (2400 W⋅m− 1⋅K− 1), reflecting its advantage to be used for the next-frontier devices. Over the past three decades, due to the continuous development of diamond film growth and doping technologies, diamond-based electronic devices have been emerging. For example, recent studies show that diamond field effect transistors (FETs) have achieved the maximum drain current over 1.35 A⋅mm− 1, the breakdown voltage over 2 kV, the cutoff frequency of 103 GHz and 120 GHz, and the microwave output power of 3.8 W⋅mm− 1 at 1 GHz.

However, the most of previous studies of diamond FETs with either doping or surface conductivity have been focused on the planar or two-dimensional (2D) architecture. At present, there is still a lack of preliminary exploration on diamond FETs with a three-dimensional (3D) architecture, which has been evidenced as a promising approach to overcome the limitations of conventional 2D architectures. For

instance, among the various 3D structures investigated recently, the gate-all-around (GAA)-based silicon nanowire, which is positioned at the end of the roadmap and has been applied in a range of uses, has shown the strongest gate controllability to effectively suppress short-channel

effects. Leveraging 3D integration for gate length and contact

area scaling, GAA nanowire transistors can circumvent process challenges such as obtaining an abrupt shallow doping gradient at the source/drain junction. Therefore, 3D vertical GAA diamond transistors on nanoscale are worth exploring.

Considering the uniqueness of diamond itself, however, the extreme hardness and chemical inertness of diamond make it difficult to be structured to a desired nanostructure. So far, considerable efforts have been made to prepare diamond nanostructures by post growth etching, but it is still of great interest to develop a low-cost, versatile, and applicable method to obtain diamond nanostructures for the practical device applications. In addition, there are still some problems to

limit the practical application of 3D GAA transistors, such as the difficulty of device processing and the complexity of 3D interconnection of electrodes.

Compound Semiconductor (Xiamen) Technology Co., Ltd is an advanced semiconductor manufacturing technology based joint venture company invested from the Korea, China and Singapore, registered in the city of Xiamen, China.

We have equipped with advanced semiconductor manufacturing tools including MPCVD, MOCVD, LPCVD, HVPE and high temperature PVD to produce high quality Diamond wafer, diamond heat sink and AlN template on various substrate including Si, sapphire, and polished diamond. Our mission is to be the most advanced compound semiconductor company in the global market, contributing to the related technology development. We have strong R&D team and actively collaborate with best research group around the world.

Currently, we are providing the thermal grade polycrystalline diamond, which can be used as an effective heat sink aims to solve the heat issue in temperature sensitive device, such as power devices, lasers and avalanche photodiodes etc. We also provides wafer scale polished diamond with sub-nanometer RMS surface roughness, which might be suitable for the integration of GaN, GaO and AlN epilayers and devices on Diamond via direct bonding or heteoepitaxy.